Low-power delta-sigma modulators are key building blocks in a variety of electronic systems, and especially those which require battery operation. Achieving low power generally requires a tradeoff between power and linearity.
A continuous-time delta-sigma architecture is commonly used to achieve low power. This style of architecture commonly uses either an active-RC integrator (FIG. 1) or Gm-C style of integrator (FIG. 2) to implement the loop transfer function.
Referring to FIG. 1, a known active-RC integrator 30 with an opamp 31 to drive resistive loads is shown. The active-RC integrator 30 achieves good linearity due to feedback from the output of the opamp 31 to its input which makes the input voltage at the opamp 31 very small. However, using feedback inside of the integrator requires additional bandwidth to drive impedances (e.g. possibly requiring a two-stage opamp) while keeping good phase-margin. Accordingly, additional power is required to drive the feedback network with sufficient loop gain and phase-margin to settle in a given amount of time.
Referring to FIG. 2, a Gm-C integrator 40 with a single stage is generally shown. A Gm cell 41 drives a capacitive load 42 without feedback from the output of the Gm cell 41 to its input and thus consumes less power than the active-RC integrator 30. In FIG. 2, the capacitive load 42 results in a voltage across the capacitor being an integral of the current applied to it. However, the Gm-C integrator 40 achieves poor linearity as a result of the large swing present at the input of the Gm cell 41. Furthermore, the supply voltage of the Gm cell 41 typically limits the maximum allowable swing at its input, restricting the utility of the Gm-C integrator 40.
Furthermore, in conventional continuous-time delta-sigma modulators, the delay through the quantizer and finite bandwidth through the integrators creates excess loop delay through the feedback loop which needs to be compensated for in order to maintain the stability of the closed loop response.
To implement the Gm cell 41 in a differential mode at low supply voltages a common-mode feedback circuit 185 is required is generally shown in FIG. 4. An example of a prior art method to establish the correct common-mode voltage setting (VCMFB in FIG. 18) is shown in FIG. 4. In FIGS. 4, M9 and M10 are designed to have the same VDSAT as MP1 and MP2. To minimize the noise contribution of MP1 and MP2, MP1 and MP2 generally should have a large VDSAT. If the supply voltage of the Gm cell VDD however is low, the large VDSAT requirement can result in node 801 and/or 802 being so low that at least one of M3, M4, M5, or M6 enters the triode region thus significantly reducing the gain of the common-mode-feedback circuit of FIG. 4.
Referring to FIG. 3, a generic prior art continuous-time delta-sigma modulator is shown at 50. Typically excess loop delay is compensated by adding an additional digital-to-analog converter (DAC) 51 which feeds back a quantized signal from the output of the quantizer 52 to its input. As shown, the design of the extra DAC 51 facilitates the excess loop delay compensation and adds extra complexity and design time to the design of the modulator 50.
Referring to FIG. 5, an implementation of a prior art circuit to recursively use a delta-sigma modulation to improve the suppression of the quantization error, namely the MASH (Multi-stAge noise-SHaping) approach is shown generally at 600. In a MASH architecture the quantization noise is estimated by subtracting the input of the quantizer from an analog representation of its output using an additional DAC 601 and a circuit 603 to subtract the output of the additional DAC 601 from the quantizer input. The resultant error is an estimate of the quantization noise and is fed to a subsequent delta-sigma ADC 600, and the outputs from the ADCs combined through a DSP 602.